Given increased density and large-scale integration requiring more efficient use of area on a chip, device sizes are continuing to decrease. For example, devices are progressing toward the 7 nm node and beyond. Shrinking transistor sizes have led to aggressive scaling of pitches, such that device characteristics and performance are influenced by physical layout. For example, it has been recognized that advanced complementary metal oxide semiconductor (CMOS) scaling has been limited by middle-of-the-line (MOL) and back-end-of-the-line (BEOL) interconnects.
Although technology scaling is increasingly smaller, chip sizes are not being reduced with the same functionality due to restricted layout styles. For example, gate contacts (CBs or CB contacts) over active regions/areas (RXs), which can result in electrical shorts between gate and contacts to source/drain regions (“diffusion contacts” or “trench silicide (TS) contacts”), are not being used since such a layout can result in decreased contact reliability.
There is a need, therefore, for improved contact layout in an integration scheme which enables chip area scaling while maintaining functionality.